Interconnect Engineering Inc. provides signal integrity simulation, schematic review and printed-circuit-board layout review services with the goal of reducing EMI potential, closing all board/system-level timing issues and ensuring general robustness of the product design. Pro-active design methodologies that include early incorporation of simulation and design review will always be the most productive solutions.
Companies who require solutions to reliability problems involving signal integrity, timing and EMI can also benefit at anytime during the design phase of the product. SiSoft QSI-300 - Extremely accurate tool for analyzing all types of interfaces such as DDR2/DDR3, for signal integrity, timing and back annoated layout data for many layout tools. Full 3D extracted traces, vias, component pads, packages, connectors, etc. can occur.
There is no better way to extract what exists on the PCB up to 40GHz. This tool also can simulate each power supply voltage for correct plane shape design to avoid plane resonance.
Companies who require solutions to reliability problems involving signal integrity, timing and EMI can also benefit at anytime during the design phase of the product. SiSoft QSI-300 - Extremely accurate tool for analyzing all types of interfaces such as DDR2/DDR3, for signal integrity, timing and back annoated layout data for many layout tools. Full 3D extracted traces, vias, component pads, packages, connectors, etc. can occur.
There is no better way to extract what exists on the PCB up to 40GHz. This tool also can simulate each power supply voltage for correct plane shape design to avoid plane resonance.
Services
Interconnect Engineering is an independent consulting company.
Interconnect Engineering was founded by Stephen Zinck in 2002.
Stephen has over 22 years of high-speed design experience ranging from hardware design to ASIC design.
He has designed numerous high-speed backplanes, switch cards and line cards for companies that range from startups to Fortune 500 companies.
He has come to the aid of several companies when "things just aren't working quite right".
He truly enjoys the field of signal integrity and tries to bring excitement to the field of signal integrity, engineering and science in general.
Interconnect Engineering was founded by Stephen Zinck in 2002.
Stephen has over 22 years of high-speed design experience ranging from hardware design to ASIC design.
He has designed numerous high-speed backplanes, switch cards and line cards for companies that range from startups to Fortune 500 companies.
He has come to the aid of several companies when "things just aren't working quite right".
He truly enjoys the field of signal integrity and tries to bring excitement to the field of signal integrity, engineering and science in general.
Before a project begins in earnest, advice and direction will be provided to remove potential barriers to achieving a successful architectural design.
High-speed connector evaluation/research for designs (backplane, card-to-card, etc.) in order to meet system level performance goals for the first generation and beyond.
ASIC I/O simulation.
All I/O specific attributes such as I/O type, drive strength, slew rate, etc. can be analyzed before a costly spin of an ASIC is committed to fabrication.
High-speed connector evaluation/research for designs (backplane, card-to-card, etc.) in order to meet system level performance goals for the first generation and beyond.
ASIC I/O simulation.
All I/O specific attributes such as I/O type, drive strength, slew rate, etc. can be analyzed before a costly spin of an ASIC is committed to fabrication.
Interconnect Engineering can provide schematic design support in addition to signal integrity simulation.
Schematic review with emphasis on good signal integrity design and EMI reduction techniques.
General review using device datasheets to find potential design flaws such as address mapping, bi-directional I/O interface issues, etc.
Schematic review with emphasis on good signal integrity design and EMI reduction techniques.
General review using device datasheets to find potential design flaws such as address mapping, bi-directional I/O interface issues, etc.
Interconnect Engineering can provide layout design support in addition to signal integrity simulation.
Once Interconnect Engineering has simulated all of the interfaces, layout rules can be generated and step-by-step layout support can be employed to ensure the layout is correct.
This will off-load your design team's responsibilities so they can move on to the next design task.
General placement will be reviewed to ensure proper placement with respect to signal integrity and timing goals.
Once Interconnect Engineering has simulated all of the interfaces, layout rules can be generated and step-by-step layout support can be employed to ensure the layout is correct.
This will off-load your design team's responsibilities so they can move on to the next design task.
General placement will be reviewed to ensure proper placement with respect to signal integrity and timing goals.
In general, the design practices used to ensure good signal integrity and timing design will go a long way towards ensuring acceptable EMI and RFI limits are not exceeded.
Use of general signal integrity principals such as termination of all transmission lines, etc.
Use of highly accurate EMI analysis can be provided using Ansoft HFSS.
This tool has the ability to simulate radiated fields from any 3D model.
Works very well with mechanical CAD tools such as Pro Engineer and AutoCAD.
The use of the type of tool is absolutely necessary for high-speed backplane design to analyze the parasitic L's, R's and C's of vias, packages, pads and connectors when the data-rate exceeds 5 Gbit/s.
Use of general signal integrity principals such as termination of all transmission lines, etc.
Use of highly accurate EMI analysis can be provided using Ansoft HFSS.
This tool has the ability to simulate radiated fields from any 3D model.
Works very well with mechanical CAD tools such as Pro Engineer and AutoCAD.
The use of the type of tool is absolutely necessary for high-speed backplane design to analyze the parasitic L's, R's and C's of vias, packages, pads and connectors when the data-rate exceeds 5 Gbit/s.
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